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authorVladimir Azarov <avm@intermediate-node.net>2025-08-11 01:58:25 +0200
committerVladimir Azarov <avm@intermediate-node.net>2025-08-11 01:58:25 +0200
commit512985277bf70e425ab6e96b3aea69ba91426afc (patch)
tree01c2326749caa9616947e995d87686fc86223713 /il.sig
parent66665caf9da212c121c99de95a18e6ae3470cdbc (diff)
Removal of register reassignment in allocator
Diffstat (limited to 'il.sig')
-rw-r--r--il.sig2
1 files changed, 1 insertions, 1 deletions
diff --git a/il.sig b/il.sig
index 4136222..4705c1b 100644
--- a/il.sig
+++ b/il.sig
@@ -92,5 +92,5 @@ signature IL = sig
strlits: int list
}
- val createCtx: P.progInfo -> ctx
+ val createCtx: P.progInfo -> string option -> ctx
end