From aad6f4f80e3196b052e96176ff412ddb7ceb7ef6 Mon Sep 17 00:00:00 2001
From: Vladimir Azarov <avm@intermediate-node.net>
Date: Mon, 11 Aug 2025 23:11:32 +0200
Subject: Mul/Div by constant transformation

---
 emit.fun | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'emit.fun')

diff --git a/emit.fun b/emit.fun
index 6b8ceb2..90cbaa2 100644
--- a/emit.fun
+++ b/emit.fun
@@ -200,12 +200,12 @@ functor Emit(I: IL) = struct
             val p = SpOrd (ord c)
             val l = collectStr cs []
           in
-            if null acc then l else SpStr (implode $ rev acc) :: p :: l
+            if null acc then p :: l else SpStr (implode $ rev acc) :: p :: l
           end
         | collectStr [] acc =
             if null acc then [] else [SpStr (implode $ rev acc)]
 
-     fun printPart (SpStr s) out = Printf out `"'" `s `"'" %
+     fun printPart (SpStr s) out = Printf out `"\"" `s `"\"" %
        | printPart (SpOrd v) out = Printf out I v %
 
      fun printStr [] = ()
@@ -1496,19 +1496,19 @@ functor Emit(I: IL) = struct
 
     val () = assertSize is81 is82 is83
 
-    val (first, second) =
-      case (t2, t3) of
-        (VtReg _ | VtStack _, _) => (t3, t2)
-      | (_, VtReg _ | VtStack _) => (t2, t3)
-      | (_, _) => raise Unreachable
+    val (pre, right) =
+      case t3 of
+        VtReg _ | VtStack _ => ([], t3)
+      | VtConst c => ([movRV is81 Rcx c], VtReg Rcx)
+      | VtUnk => raise Unreachable
   in
-    [
+    pre @ [
+      mov is81 (VtReg Rax) t2,
       if signExtend then
         if is81 then "cqo" else "cdq"
       else
         "xor edx, edx",
-      mov is81 (VtReg Rax) first,
-      sprintf `op' `" " A2 prm is81 second %,
+      sprintf `op' `" " A2 prm is81 right %,
       mov is81 t1 (VtReg resInReg)
     ]
   end
-- 
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